This invention relates to testing integrated circuits, and more particularly, to testing integrated circuits that contain blocks of identical circuitry.
Modern integrated circuits require testing to verify that they are properly performing their intended functions. A logic circuit may be tested by observing its response to test vectors. If the observed response matches the expected response, the circuit passes the test.
Testing tools called automatic test pattern generation (ATPG) tools are used to generate the test data needed to thoroughly test a circuit. Completely exhaustive testing, while theoretically possible, is typically not efficient or warranted. Rather, an ATPG tool attempts to generate a meaningful set of test data that will exercise the relevant features of the circuit under test. In a typical scenario, an ATPG tool is provided with a netlist describing a given integrated circuit. The ATPG tool processes the netlist and generates a corresponding set of test data. The test data is applied to the circuit under test using a tester. The tester evaluates the resulting output of the circuit to determine whether the circuit is performing properly.
If a circuit is large and complicated, the ATPG tool may crash (if sufficient computer memory is not available) or may take an undesirably long time to complete the test data generation process.
It would therefore be desirable to be able to provide ways in which to improve automatic test pattern generation processing of integrated circuit netlists to produce test data.